Every Wire Is an RLC Circuit: Why Your Digital Signal Rings

There is no such thing as a digital signal at the physical layer. The clean trapezoid you draw on a whiteboard — flat low, sharp rising edge, flat high — is a fiction your oscilloscope never sees. What it sees instead is a smear of overshoot, ringing, and little reflected ghosts that arrive too late. Engineers call these problems "signal integrity" and treat them as a separate, intimidating discipline with its own black-magic reputation. They are not separate. They are the step response of a second-order circuit you already know, run at picosecond timescales.

Here is the claim worth testing as you read: every copper trace on a printed circuit board (PCB) is a resistor, an inductor, and a capacitor wired in series — an RLC circuit. Drive it with a logic edge and you are not sending a "1". You are kicking an underdamped resonator and watching it ring down. The overshoot, the ringing, the reflections that plague high-speed design are not noise to be filtered out. They are the lumped RLC step response, the same transient you'd analyse in a first-year circuits course, sped up by a factor of a billion.

Why a wire has L and C (and a little R)

Start with the offending claim: a wire is not a wire. A length of copper is a conductor, and every conductor carrying a changing current has two unavoidable parasitic personalities.

It has inductance, because current flowing through it sets up a magnetic field, and a changing current means a changing field, and a changing field induces a back-EMF (electromotive force) that opposes the change. That opposition is exactly what an inductor does. A straight trace over a ground plane carries on the order of a few nanohenries per centimetre — tiny, but $V = L\,\frac{di}{dt}$ scales with how fast the current changes, and a 50-picosecond edge changes current very fast.

It has capacitance, because the trace and the ground plane beneath it are two conductors separated by a dielectric — which is the definition of a capacitor. A signal trace over a return plane stores charge across that gap, on the order of 1 picofarad per centimetre. Every gap between two conductors is a capacitor whether you drew one or not.

And it has a little resistance — the copper isn't superconducting, and at high frequencies the current crowds into the outer skin of the conductor (the skin effect), raising the effective resistance further. Resistance is the smallest of the three personalities, but it is the one that decides whether the circuit rings or settles, so it earns its place.

The lumped model: a trace is a series RLC, the edge is a step

Take the simplest honest model. Lump the trace's total inductance into one $L$, its total capacitance into one $C$, and its loss into one $R$, in series. A logic gate switching from low to high applies a voltage step across this network. The capacitor voltage — which is what the receiving gate actually reads — obeys a second-order linear differential equation, the same one that governs a mass on a spring or a pendulum:

$$\frac{d^2 v_C}{dt^2} + 2\zeta\omega_0\,\frac{dv_C}{dt} + \omega_0^2\,v_C = \omega_0^2\,V_{step}$$

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Two numbers control everything. The natural frequency $\omega_0$ sets how fast the circuit wants to oscillate, and the damping ratio $\zeta$ sets whether it actually does. Both come straight from the component values:

$$\omega_0 = \frac{1}{\sqrt{LC}}, \qquad \zeta = \frac{R}{2}\sqrt{\frac{C}{L}}$$

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When $\zeta < 1$ the circuit is underdamped: the step response overshoots and rings at the damped frequency $\omega_d = \omega_0\sqrt{1 - \zeta^2}$, the oscillation decaying under an envelope $e^{-\zeta\omega_0 t}$. When $\zeta = 1$ it is critically damped: the fastest possible rise with no overshoot at all. When $\zeta > 1$ it is overdamped: slow and sluggish, no ring but no speed either. Go back to the lab and watch the regimes change as you drag $R$ — you are sliding $\zeta$ directly, since $\zeta$ is linear in $R$.

The single most useful fact a digital designer can carry around is the relationship between damping and overshoot. The peak overshoot of an underdamped step response, as a fraction of the step height, is:

$$M_p = \exp\!\left(\frac{-\pi\zeta}{\sqrt{1-\zeta^2}}\right)$$

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Plug in numbers and the picture sharpens. A damping ratio of $\zeta = 0.5$ gives 16% overshoot. $\zeta = 0.3$ gives 37%. $\zeta = 0.1$ — a lightly damped trace — overshoots by a punishing 73%, meaning a 3.3-volt edge briefly swings to 5.7 volts. That is enough to forward-bias a protection diode, false-trigger a downstream input, or, repeated billions of times, slowly wear out a gate oxide.

ζ = 0.5

16%

overshoot — a comfortable margin

ζ = 0.3

37%

overshoot — getting risky

ζ = 0.1

73%

overshoot — a 3.3 V edge hits 5.7 V

When the lumped model fails: reflections and the distributed line

The lumped RLC model explains ringing, but it quietly assumes the whole trace switches at once — that the signal at the far end is the same as the signal at the near end, just delayed. That assumption holds only while the trace is electrically short: short enough that the edge takes negligible time to traverse it compared to how long the edge itself lasts.

Signals propagate down a PCB trace at roughly half the speed of light, about 15 cm/ns. So an edge with a 50-picosecond rise time has a physical "length" of only about 7.5 mm of trace — the spatial extent of the rising slope as it travels. Once your trace approaches that scale, the near end has already finished switching before the far end has heard about it, and you can no longer treat the wire as one lumped circuit. It becomes a distributed system — a transmission line, an infinite ladder of tiny series-$L$, shunt-$C$ segments — and its defining number is its characteristic impedance $Z_0 = \sqrt{L/C}$, the ratio it presents to a travelling wave.

The rule of thumb that tells you which world you're in:

$$\ell_{crit} \approx \frac{t_r \cdot v}{2}$$

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A trace longer than $\ell_{crit}$ is "long" and must be treated as a controlled-impedance line; shorter than that, the lumped RLC model is fine. For that same 50-picosecond edge, $\ell_{crit}$ works out to about 3.75 mm — half the edge's spatial length. The factor of 2 is the key: it's the round trip. A wave has to travel down the line and reflect back before the reflection matters, so the threshold is set by twice the one-way delay. Different references put the constant anywhere from a sixth to a half of the rise length; the exact fraction is a judgement call about how much ringing you tolerate, not a law.

That reflected amplitude has a name and a formula. At any junction where the line impedance $Z_0$ meets a load impedance $Z_L$, the fraction of the wave that reflects is:

$$\Gamma = \frac{Z_L - Z_0}{Z_L + Z_0}$$

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A matched load ($Z_L = Z_0$) gives $\Gamma = 0$: the wave is fully absorbed, nothing comes back. An open ($Z_L = \infty$) gives $\Gamma = +1$: total reflection, same sign. A short ($Z_L = 0$) gives $\Gamma = -1$: total reflection, inverted. Every CMOS (complementary metal-oxide-semiconductor) input is a high-impedance, mostly-capacitive load — close to an open — so an unterminated high-speed line reflects nearly all the energy back at the driver, where it reflects again off the driver's own impedance mismatch, and the bus rings.

The three villains are one phenomenon

Signal-integrity courses present three separate monsters, each with its own chapter and its own dread. Reframed through the RLC lens, they collapse into one second-order story told in three accents.

Ringing is the underdamped step response of equation (1). The trace's $L$ and $C$ form a resonator; the logic edge is the step; $\zeta < 1$ means it rings. There is no second mechanism — it is literally the lab at the top of this page.

Ground bounce is $V = L\,\frac{di}{dt}$ applied to the return path. When many outputs switch at once, a large current swings through the shared inductance of the ground and power connections, develops a voltage across that lead inductance, and the chip's internal ground reference momentarily lifts off the board ground. Same $L$, same $\frac{di}{dt}$, same physics as the inductive term in the RLC circuit — just measured on the ground pin instead of the signal pin.

Reflections are $\Gamma$ at a mismatch, equation (5). The distributed version of the same energy that, in the lumped model, sloshed between $L$ and $C$. A reflection is a ring whose period is set by the round-trip line delay rather than by $\sqrt{LC}$.

Every wire is an RLC circuit; signal integrity is just that step response run at 10 GHz.

Three names, three chapters, one underdamped second-order system. Once you see that ringing, ground bounce, and reflections are the same energy expressed through $L$, $\frac{di}{dt}$, and $\Gamma$, the discipline stops being a bestiary of black magic and becomes a single equation you can reason about.

The cures: damp it, match it, or slow it down

If the disease is an underdamped, mismatched second-order system, the cures are exactly the three knobs in equations (2), (3), and (5).

Slow the edge. Overshoot only happens because the edge contains frequencies near $\omega_0$. A slower rise time excites less of the resonance; in the critical-length rule of equation (4), a longer $t_r$ raises $\ell_{crit}$ so more of your traces stay "short." This is why driver chips offer slew-rate control — deliberately blunting the edge is often the cheapest fix. The cost is bandwidth: you cannot ring a bell you tap gently, but you also cannot ring it fast.

Add damping. A series resistor near the driver raises $R$, which raises $\zeta$ in equation (2), which crushes the overshoot in equation (3). This is series termination: a resistor chosen so the driver's output impedance plus the resistor equals $Z_0$, absorbing the reflection when it returns. It is the most direct application of "drag $R$ to the right" in the opening lab.

Match the impedance. End the line in a load equal to $Z_0$ and equation (5) gives $\Gamma = 0$ — no reflection, ever. This is the gold standard: route every high-speed trace as a controlled-impedance line (a fixed $Z_0$, usually 50 Ω, set by trace width and dielectric height) and terminate it in its own impedance. The reflection problem disappears not by fighting it but by removing the mismatch that caused it.

Cross-field: every wire is a control system

The deepest payoff of the RLC reframing connects signal integrity to a field that looks, on the surface, unrelated: control theory.

Equation (1) — the second-order ODE with damping ratio $\zeta$ and natural frequency $\omega_0$ — is the defining equation of a second-order control loop. The overshoot formula in equation (3) is the one a control engineer uses to tune a PID (proportional-integral-derivative) controller. The phase-locked loop (PLL) that recovers your clock is a second-order feedback system with exactly the same step response. They are all the same mathematics wearing different costumes.

That means the intuition transfers in both directions. A PID controller pushed to high gain overshoots and oscillates — and so does a trace with too little series resistance. A PLL that's underdamped rings before it locks — and so does an unterminated bus. If you have tuned a control loop, you already know how to damp a wire; if you have terminated a transmission line, you already know how to stabilise a feedback loop. The labs make the equivalence concrete: the PID tuner, the PLL lock-in, and the RLC resonance lab at the top of this page are the same second-order step response driven from three different desks.

So the final reframing is the title taken one step further: every wire is an RLC circuit, and every RLC circuit is a control system. The flat trapezoid was never real. What's real is a damped resonator settling toward its setpoint, and your job as a high-speed designer is the control engineer's: pick $\zeta$ so it gets there fast, without overshooting, every single edge, a billion times a second.

Reading further

• Bogatin, Signal Integrity — Simplified, ch. 8 (Prentice Hall) — the canonical text that builds the whole field up from the lumped RLC model and the transmission-line picture; start here if you want the physical intuition before the math.
• Johnson & Graham, High-Speed Digital Design: A Handbook of Black Magic (Prentice Hall) — the practitioner's bible on ringing, ground bounce, and termination, written as field-tested rules of thumb rather than derivations.
• Pozar, Microwave Engineering, 4th ed., ch. 2 (Wiley) — the rigorous derivation of transmission lines, the reflection coefficient $\Gamma$, and characteristic impedance from Maxwell's equations.
• Sedra & Smith, Microelectronic Circuits (Oxford University Press) — the clean second-order treatment of the RLC step response, damping ratio, and overshoot that underpins equations (1) through (3).